Recently, as semiconductor memory devices are integrated highly, the number of memory cells are increased which are connected on a bit line. This becomes a cause of increasing the bit line loading (or capacitance). As the bit line loading becomes greater, the speed to read/write data from/into a memory cell (hereinafter, referred to as "an access speed") becomes delayed.
One approach to solve such a problem is to precharge bit lines at a predetermined voltage level before reading/writing data from/to the cell. It is general to precharge the bit lines by use of the pulse signal like an address detection (ATD) signal or a clock signal. It is to reduce current consumption and to prevent the drop of the access speed. A simplified diagram of a conventional semiconductor memory device, particularly, SRAM, with a bit line precharge scheme is illustrated in FIG. 1.
The SRAM device 1 comprises a pair of bit lines BL and BLB between which a memory cell MC for storing data information is connected. At top sides of bit lines BL and BLB, PMOS transistors M1 and M2 for bit line precharge are connected which are turned on/off by means of a top side precharge signal PTOP from an AND gate G1. The AND gate G1 receives a bank select signal BS and a first precharge control signal PPRECH1 and generates the top side precharge signal PTOP. Similarly, at bottom sides of bit lines BL and BLB, PMOS transistors M9, M10 and M11 for bit line precharge are connected therebetween which are turned on/off by means of a bottom side precharge signal PBOP from an AND gate G2. The AND gate G2 receives the bank select signal BS and a second precharge control signal PPRECH2 and generates the bottom side precharge signal PTOP.
As illustrated in the drawing, a section word line SWL connected to the memory cell MC is selected and driven by both an AND gate G3 (used as a driver) and a decoding block 10. The decoding block 10 generates section word line select signals BSLi and column select signals Yi and YiB (i=0-n) in response to the bank select signal BSi, row pre-decoder signals XPDOi and column pre-decoder signals YPDOi. The AND gate G3 has two input terminals connected to a main word line MWL and one of the signals BSLi, respectively. NMOS transistors M12 and M15 which are connected between the bit lines BL and BLB and a write driver 12 are turned on/off in accordance with the column select signal Yi. And, NMOS transistors M13 and M14 which are connected between the bit lines BL and BLB and a sense amplifier 14 are turned on/off in accordance with the column select signal YiB complementary to the signal Yi.
An operation of the semiconductor memory device 1 will be explained below with reference to FIG. 2, which is a timing diagram for describing a bit line precharge operation. Before the activation of the section word line, a bit line precharge operation is performed as follows.
Since the block select signal BSn and the top and bottom precharge control signals PPRECH1 and PPRECH2 are low, the AND gates G1 and G2 makes the top and bottom precharge signals PTOPn and PBOPn low. This enables the PMOS transistors M1, M2, and M9 to M11 to be turned on, and then the bit lines BL and BLB are precharged.
As shown in FIG. 2, the signals MWLn, BSn, XPDOn, YPDOn, PPRECH1 and PPRECH2 transition from low to high. First, the top and bottom precharge signals PTOPn and PBOPn go high through the AND gates G1 and G2, and the PMOS transistors M1, M2, and M9 to M11 are turned off. And then, the decoding block 10 responds to the signals BSn, XPDOn and YPDOn, which makes one of the selection word line select signals BSLi high, so that the section word line SWLn is activated through the AND gate G3. Furthermore, the decoding block 10 activates the column select signal Yn high and the column select signal YnB low, so that the bit lines BL and BLB are connected to the write driver 12 and the sense amplifier 14. After this, reading/writing may be performed according to the manner well known in the art.
When the signals BSn, PPRECH1 and PPRECH2 transition from high back to low, the top and bottom precharge signals PTOPn and PBOPn become low again. This enables the PMOS transistors M1, M2, and M9 to M11 to be turned on, so that the bit lines BL and BLB are precharged for the next reading/writing operation. And, the decoding block 10 inactivates the column select signal Yn low and the column select signal YnB high, so that the bit lines BL and BLB are separated from the write driver 12 and the sense amplifier 14.
It would be ideal if the period of the inactivation (activation) of the top and bottom precharge signals corresponds to the period of the activation (inactivation) of the section word line. That is, when the bit lines are precharged the section word line is inactivated, and when the section word line is activated the bit lines don't become precharged, which would be accomplished if the bit lines had a high impedance.
As illustrated by time interval t.sub.over in FIG. 2, however, since the period of the inactivation (activation) of the top and bottom precharge signals overlaps with the period of the activation (inactivation) of the section word line (for example, owing to voltage/temperature variation, and to different signal transfer path), the bit line precharge time may become long. This is because the top and bottom precharge signals PTOP and PBOT don't track the selection word line and the column select signal. As a result, the bit line precharge speed is delayed, causing the drop of the access speed.